loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 813.out
1 GPR0 0000000000000040
2 GPR1 0000000000000000
3 GPR2 0000000300000003
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFF0980
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000020000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000001
15 GPR14 FFFFFFFFE0000000
16 GPR15 FFFFFFFFFFFFFFFF
17 GPR16 000000000000FFFD
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFFFFFFFFF
20 GPR19 0000000000000001
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFF0980
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 0000000009CED980
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFF8001FFF
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 000000000001C020
32 GPR31
33 CR 000000003BD54495
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000000
37