loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 82.out
1 GPR0 00008E5500008E4E
2 GPR1 FFFFFFFFFFFFFFFF
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 50B079A40FFF6E00
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 000000000FFFFFFF
10 GPR9 0000021FFFFFFFE1
11 GPR10 0000000000001454
12 GPR11 0000000051509091
13 GPR12 0000000000000000
14 GPR13 0000380380000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 00000000FE07FF01
18 GPR17 0000000000000000
19 GPR18 00000000FE07FF00
20 GPR19 0000000051509092
21 GPR20 0000000000001454
22 GPR21 0001C01B10932308
23 GPR22 0000000000000000
24 GPR23 000000015FFFFFEA
25 GPR24 0000000051509092
26 GPR25 0000000000000000
27 GPR26 0000000051509092
28 GPR27 0000000000000000
29 GPR28 0000000000000016
30 GPR29 FFFFFFFFEEB1FFFF
31 GPR30 00000000B119001B
32 GPR31
33 CR 000000005150919A
34 LR 0000000000000000
35 CTR 000000000FFFFFFF
36 XER 0000000080007FB4
37