loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 820.out
1 GPR0 000000000001C020
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 000000000000000E
5 GPR4 FFFFFFFFFFFFFFBF
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 000000000A900000
8 GPR7 0000000000000000
9 GPR8 00000000001FF000
10 GPR9 0000000000000000
11 GPR10 000000000001C034
12 GPR11 0000000000000000
13 GPR12 0000000000000608
14 GPR13 FFFFFFFFFFFFFFFF
15 GPR14 FFFFFFFFFFFFFFFF
16 GPR15 002A6D10A9A9E47A
17 GPR16 0000000000000000
18 GPR17 0000000000000001
19 GPR18 0000000000000000
20 GPR19 002A6D10A9A8245A
21 GPR20 FFFFFFFFFFFE3F9F
22 GPR21 0000000000000040
23 GPR22 0000000000000000
24 GPR23 000000000A900000
25 GPR24 FFFFFFFFFFE00FFF
26 GPR25 FFFFFFFFFFFFFFFF
27 GPR26 0000000000000000
28 GPR27 000000000001C020
29 GPR28 FFFFFFFFFFFFFFFF
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 000000003779AB29
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000031
37