loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 824.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 FFFFFFFFFFFFFF00
4 GPR3 0000000000000000
5 GPR4 000000005099D032
6 GPR5 0000000000000000
7 GPR6 000000000001C020
8 GPR7 FFFFFFFFFFFFFFF6
9 GPR8 000000000A1339FE
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 000000000000CA80
15 GPR14 000000000A1339FE
16 GPR15 000000000034276A
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 FFFFFFFFFFFFFF2B
22 GPR21 000000005099CFF2
23 GPR22 000000000000E77A
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000008
28 GPR27 0000000080000000
29 GPR28 0000000000000000
30 GPR29 FFFFFFFFFFFFFFED
31 GPR30 FFFFFFFFAF4C1958
32 GPR31
33 CR 000000000099E400
34 LR 0000000000000008
35 CTR 0000000000000000
36 XER 0000000000000000
37