loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 829.out
1 GPR0 0000000000009894
2 GPR1 000000000001C01C
3 GPR2 0000000000000000
4 GPR3 FFFFFFFFFFFFFFFE
5 GPR4 0000000000000000
6 GPR5 000000000000145E
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFFE9
9 GPR8 0000000000010020
10 GPR9 0000000000000020
11 GPR10 0000000000000000
12 GPR11 FFFFFFFFFFFEFFDF
13 GPR12 000000000001C020
14 GPR13 0000000000000000
15 GPR14 000000000000E010
16 GPR15 FFFFFFFF9341FC20
17 GPR16 0000000000000000
18 GPR17 0000000000000005
19 GPR18 000000000001C021
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 000000000001C020
23 GPR22 0000000000000000
24 GPR23 FFFFFFFFFFFEFFDF
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000014608BC0
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000090095050
34 LR 000000000001C020
35 CTR FFFFFFFFFFFFFFE9
36 XER 00000000A0040000
37