loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 886.out
1 GPR0 FFFFFFFFFFFFFFFF
2 GPR1 0000000A0000000A
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 000000000000000B
10 GPR9 0000140000001400
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000020
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 FFFFFFFFE5A60000
19 GPR18 FFFFFFF5FFFFFFFF
20 GPR19 0000000009000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFD600000017
23 GPR22 0000000099D55919
24 GPR23 FFFFFFFFFFFFFF80
25 GPR24 FFFFFFFFFFFFFFFF
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000039DD5519
34 LR 000000000001C020
35 CTR FFFFFFFFFFFFD7E1
36 XER 00000000C0080000
37