loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 892.out
1 GPR0 2180000FFFFFFFFF
2 GPR1 0000000000000002
3 GPR2 002705A3F0B30000
4 GPR3 000000008001C008
5 GPR4 0000000000000000
6 GPR5 0000000000000020
7 GPR6 000000008001C008
8 GPR7 FFFFFFFFFFFF1861
9 GPR8 0000000000000000
10 GPR9 FFFFFFFF506E3FF7
11 GPR10 FFFFFFFEFFFC7FEF
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 FFFFFFFEFFFB9850
15 GPR14 0000000000000040
16 GPR15 FFFFFFD8FA5C0F4C
17 GPR16 0000000000000C31
18 GPR17 000000000000E79D
19 GPR18 FFFFFFFFFFFE7FEF
20 GPR19 0000000000000002
21 GPR20 0000000000000000
22 GPR21 DE7FFFF000000000
23 GPR22 FFFFFFFFFFFD5C92
24 GPR23 2000000020000020
25 GPR24 0000000000000001
26 GPR25 000000000000002D
27 GPR26 000000000001C030
28 GPR27 FFFFFFFFFFFE3FD0
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 000000000001C020
32 GPR31
33 CR 00000000505B3B59
34 LR 000000000000E79D
35 CTR FFFFFFFF506E3FF7
36 XER 000000008001C008
37