loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 903.out
1 GPR0 0000000000000000
2 GPR1 00000000FFFE3FE0
3 GPR2 0000000000000040
4 GPR3 0000000000000000
5 GPR4 000000001C180C00
6 GPR5 0000000000008090
7 GPR6 0000002D67A20243
8 GPR7 0000000000000400
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 0000000008070604
11 GPR10 0000000000000000
12 GPR11 FFFFFFFFFFFFFFFF
13 GPR12 0000000000000000
14 GPR13 FFFFFFFFFFFF7B6F
15 GPR14 0000000000000400
16 GPR15 0003FFFE00000000
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 0000000000000040
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 0000000000000040
23 GPR22 0000000000000000
24 GPR23 0000000000000000
25 GPR24 FFFFFFDFE3E7F400
26 GPR25 0000000000000000
27 GPR26 FFFFBFB7FFFFBFB7
28 GPR27 0007FFFFF7F8F9FD
29 GPR28 0000000067A20243
30 GPR29 0000000005A26000
31 GPR30 0000000008070603
32 GPR31
33 CR 0000000050845454
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000080000000
37