loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 922.out
1 GPR0 000000000000007E
2 GPR1 0000000000000000
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 FFFFFFFFFFFFFDFF
5 GPR4 FFFFFFFFFFFFFFFF
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 0000000000003EB1
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000200
16 GPR15 0000000000000000
17 GPR16 0000000000000001
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFFFFFFFFF
20 GPR19 0000000000003EB1
21 GPR20 000000000000592D
22 GPR21 0000000000000000
23 GPR22 0000000000003EB1
24 GPR23 0000000000000000
25 GPR24 FFFFFFFFFFFFFFFF
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 0000000000000000
29 GPR28 FFFFFFFFFFFFFFFF
30 GPR29 000000000001C020
31 GPR30 000000000000001F
32 GPR31
33 CR 0000000039925569
34 LR 0000000000000000
35 CTR F555555555555555
36 XER 00000000A007D1CD
37