loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 934.out
1 GPR0 FFFFFFFFFFE1FFDF
2 GPR1 0000000000000000
3 GPR2 0000000000000000
4 GPR3 0000000000000005
5 GPR4 FFFFFFFFFFFFFFFF
6 GPR5 0000000000000000
7 GPR6 00000000007F0000
8 GPR7 0000000030000000
9 GPR8 000000E01000C000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 00000000007F0000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 000000001FFBA330
19 GPR18 000000000001C020
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFFFFFFFFFFFFFFF
23 GPR22 FFFFFFFFFFFFFFF8
24 GPR23 3C00000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000022
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFA330
29 GPR28 000000000000074C
30 GPR29 FFFFFFFFFFFFB1FE
31 GPR30 0000000000000000
32 GPR31
33 CR 000000002D111B9C
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 0000000020040000
37