loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 939.out
1 GPR0 0000000001FFFFFF
2 GPR1 0000000000000000
3 GPR2 FFFFFFFFFFFFFBF1
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFFFF45
6 GPR5 FFFFFFFFFFFFFF95
7 GPR6 0000000000000001
8 GPR7 0000000000000000
9 GPR8 0000000000000004
10 GPR9 0000004000000040
11 GPR10 0000000000000000
12 GPR11 0000000000000005
13 GPR12 0000000000000005
14 GPR13 00000000005F8FC0
15 GPR14 0000000000000000
16 GPR15 00000FFFF47FFFFF
17 GPR16 FFFFFFFFFFFFDF00
18 GPR17 0100000000000000
19 GPR18 000000000001C01F
20 GPR19 0000000000000040
21 GPR20 FFFFFFFFFFFFFEF8
22 GPR21 0000000073540005
23 GPR22 FEFFFFFFFFFFFFFF
24 GPR23 0100000000000000
25 GPR24 0000000000000004
26 GPR25 0000000000000040
27 GPR26 000000000001C020
28 GPR27 0000000000000014
29 GPR28 00000000000000BA
30 GPR29 000000000000000F
31 GPR30 0000000000000000
32 GPR31
33 CR 000000009029DD95
34 LR 0000000000000018
35 CTR 0000000000000003
36 XER 000000008003FFA3
37