loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 947.out
1 GPR0 FFFFFFFFFFFFFFFE
2 GPR1 0000000000000000
3 GPR2 000000000000002F
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 FFFFFFFFFFFE3FD7
8 GPR7 0000000000006E5A
9 GPR8 0000000000000000
10 GPR9 0000000000000007
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000090000
14 GPR13 0000000000000000
15 GPR14 FFFFFFFFFFFFFFFC
16 GPR15 0000000000000000
17 GPR16 000000000001C020
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFFFFFFFFC
20 GPR19 0000000000000000
21 GPR20 0000000000000006
22 GPR21 0000000000000001
23 GPR22 0000000000006E5A
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000020
27 GPR26 0000000000000010
28 GPR27 FFFFFFFF00000019
29 GPR28 0000000000000000
30 GPR29 000000000000001C
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000033951BF3
34 LR 0000000000000007
35 CTR 0000000000000000
36 XER 000000008001C020
37