loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 955.out
1 GPR0 0000000000000000
2 GPR1 0000000000000101
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0000000000038040
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 FFFFFFFFFFFFFFFE
9 GPR8 000000000001C020
10 GPR9 0000000000000010
11 GPR10 0000000000000101
12 GPR11 0000000000000101
13 GPR12 0000000000000000
14 GPR13 0000000000001010
15 GPR14 0000000000000040
16 GPR15 FFFFFFFFFB7C001E
17 GPR16 0000000000000101
18 GPR17 8000000000000000
19 GPR18 0000000000000001
20 GPR19 0000000000000000
21 GPR20 FFFFFFFFFFFFFEFD
22 GPR21 00000000000001BE
23 GPR22 0000000005000000
24 GPR23 0000000000000081
25 GPR24 0000000000001010
26 GPR25 0000000000000000
27 GPR26 0000000000000101
28 GPR27 0000000000000000
29 GPR28 FFFFFFFFFFFFFFFE
30 GPR29 0000000000000000
31 GPR30 000000000001C020
32 GPR31
33 CR 000000009D9D9385
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 000000008003C204
37