loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 961.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 0000000000002A3E
4 GPR3 0000000000000000
5 GPR4 0000000000000000
6 GPR5 0000000000000000
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 FFFFFFFFFF9E1AC8
16 GPR15 000000000001C038
17 GPR16 FFFFFFFFFFFFFFFF
18 GPR17 0000000000000000
19 GPR18 FFFFFFFFC66FB5FD
20 GPR19 0000000000000000
21 GPR20 0000000000000040
22 GPR21 000000000000003F
23 GPR22 0000000039904A03
24 GPR23 000000000001C020
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 FFFFFFFFFFFFD5C2
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 0000000000000000
31 GPR30 FFFFFFFFFFFFFFFF
32 GPR31
33 CR 0000000039004A03
34 LR 0000000000000000
35 CTR 0000000000000000
36 XER 00000000A0040000
37