loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 962.out
1 GPR0 0000000000000000
2 GPR1 00000000001247D6
3 GPR2 0000000000000000
4 GPR3 0000000000000000
5 GPR4 0001181B00800000
6 GPR5 0000000000000002
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000004980000000
10 GPR9 0000000000000000
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 FFFFFFFFFFFFF41E
14 GPR13 FFFFFFFFFFFE3FDE
15 GPR14 0000000000000001
16 GPR15 0000000000000000
17 GPR16 01FFFFFFFFFFFFFF
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 00000000A0040000
21 GPR20 00000000A0040000
22 GPR21 0000000000000000
23 GPR22 FFFFFFFFFFFFFFFF
24 GPR23 0000000000000000
25 GPR24 0000000000000000
26 GPR25 0000000000000000
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFFFED
29 GPR28 FFFFFFFFFFFFFFDE
30 GPR29 FFFFFFFFFFFFFFFF
31 GPR30 0000000000000002
32 GPR31
33 CR 0000000036850094
34 LR 00000000001247D6
35 CTR 000000000000001F
36 XER 00000000E00C0000
37