loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 963.out
1 GPR0 FFFFFFFC7FFFFFE8
2 GPR1 0000000000000040
3 GPR2 FFFFFFFFFFFFFFFF
4 GPR3 0000000000000000
5 GPR4 FFFFFFFFFFFFFFFF
6 GPR5 0000000000007A79
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 FFFFFFFFFFFFFFFF
10 GPR9 FFFFFFFFFFFE3FDF
11 GPR10 0000000000000000
12 GPR11 0000000000000000
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000020
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 000000000001C020
19 GPR18 0000000000000000
20 GPR19 FFFFFFFFFFFFFFFF
21 GPR20 0000000000000000
22 GPR21 0000000000000000
23 GPR22 000000000001C020
24 GPR23 00000000000057A7
25 GPR24 0000000000000001
26 GPR25 000000007FFFFFE8
27 GPR26 0000000000000000
28 GPR27 FFFFFFFFFFFFFFFF
29 GPR28 0000000000000016
30 GPR29 00000000003803FF
31 GPR30 FFFFFFFFFFFFFFFF
32 GPR31
33 CR 0000000035099A34
34 LR FFFFFFFFFFFFFFFF
35 CTR FFFFFFFFFFFFFFFF
36 XER 0000000080000000
37