loadstore1: Improve timing of data path from cache RAM to writeback
[microwatt.git] / tests / 970.out
1 GPR0 0000000000000000
2 GPR1 0000000000000000
3 GPR2 00000000C0000000
4 GPR3 08080808F78B0808
5 GPR4 0000000000000000
6 GPR5 FFFFFFFFFFFFFFFF
7 GPR6 0000000000000000
8 GPR7 0000000000000000
9 GPR8 0000000000000000
10 GPR9 000000000001C020
11 GPR10 000000000001C030
12 GPR11 00000000FFFFC006
13 GPR12 0000000000000000
14 GPR13 0000000000000000
15 GPR14 0000000000000000
16 GPR15 0000000000000000
17 GPR16 0000000000000000
18 GPR17 0000000000000000
19 GPR18 0000000000000000
20 GPR19 0000000000000000
21 GPR20 0000000000000000
22 GPR21 FFE00001AFFFFFFF
23 GPR22 00013B13A09D89D8
24 GPR23 0000000000000000
25 GPR24 08080808F78AD3F6
26 GPR25 0000000000000000
27 GPR26 00000000FFFFC007
28 GPR27 0000000000000000
29 GPR28 0000000000000000
30 GPR29 000000000000001A
31 GPR30 0000000000000000
32 GPR31
33 CR 0000000020582889
34 LR 01FFFFFFFFFFFFFF
35 CTR 0000000000000000
36 XER 0000000000000000
37