tests/aiger/neg.ys

   1 read_verilog <<EOT
   2 module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
   3 assign c = a & b;
   4 endmodule
   5 EOT
   6 select -assert-count 1 i:a
   7 select -assert-count 1 i:b
   8 select -assert-count 1 o:c
   9 select -assert-count 3 x:* s:64 %i
  10 design -save read
  11
  12 !rm -rf neg.out
  13 !mkdir neg.out
  14 simplemap
  15 write_aiger -map neg.out/neg.map neg.out/neg.aig
  16
  17 design -reset
  18 read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
  19 select -assert-count 1 i:a
  20 select -assert-count 1 i:b
  21 select -assert-count 1 o:c
  22 select -assert-count 3 x:* s:64 %i
  23
  24
  25 design -load read
  26 !rm -rf neg.out
  27 !mkdir neg.out
  28 simplemap
  29 write_xaiger -map neg.out/neg.map neg.out/neg.aig
  30
  31 design -reset
  32 read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
  33 select -assert-count 1 i:a
  34 select -assert-count 1 i:b
  35 select -assert-count 1 o:c
  36 select -assert-count 3 x:* s:64 %i