tests/anlogic/add_sub.ys

   1 read_verilog add_sub.v
   2 hierarchy -top top
   3 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
   4 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
   5 cd top # Constrain all select calls below inside the top module
   6 select -assert-count 10 t:AL_MAP_ADDER
   7 select -assert-count 4 t:AL_MAP_LUT1
   8 select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
   9