tests/anlogic/latches.v

   1 module latchp
   2     ( input d, clk, en, output reg q );
   3         always @*
   4                 if ( en )
   5                         q <= d;
   6 endmodule
   7
   8 module latchn
   9     ( input d, clk, en, output reg q );
  10         always @*
  11                 if ( !en )
  12                         q <= d;
  13 endmodule
  14
  15 module latchsr
  16     ( input d, clk, en, clr, pre, output reg q );
  17         always @*
  18                 if ( clr )
  19                         q <= 1'b0;
  20                 else if ( pre )
  21                         q <= 1'b1;
  22                 else if ( en )
  23                         q <= d;
  24 endmodule
  25
  26
  27 module top (
  28 input clk,
  29 input clr,
  30 input pre,
  31 input a,
  32 output b,b1,b2
  33 );
  34
  35
  36 latchp u_latchp (
  37         .en (clk ),
  38         .d (a ),
  39         .q (b )
  40     );
  41
  42
  43 latchn u_latchn (
  44         .en (clk ),
  45         .d (a ),
  46         .q (b1 )
  47     );
  48
  49
  50 latchsr u_latchsr (
  51         .en (clk ),
  52         .clr (clr),
  53         .pre (pre),
  54         .d (a ),
  55         .q (b2 )
  56     );
  57
  58 endmodule