tests/anlogic/mux.ys

   1 read_verilog mux.v
   2 proc
   3 flatten
   4 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
   5 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
   6 cd top # Constrain all select calls below inside the top module
   7
   8 select -assert-count 1  t:AL_MAP_LUT3
   9 select -assert-count 4  t:AL_MAP_LUT4
  10 select -assert-count 4  t:AL_MAP_LUT5
  11 select -assert-count 1  t:AL_MAP_LUT6
  12 select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D