tests/anlogic/shifter.v

   1 module top    (
   2 out,
   3 clk,
   4 in
   5 );
   6     output [7:0] out;
   7     input signed clk, in;
   8     reg signed [7:0] out = 0;
   9
  10     always @(posedge clk)
  11         begin
  12 `ifndef BUG
  13                 out    <= out >> 1;
  14                 out[7] <= in;
  15 `else
  16
  17                 out    <= out << 1;
  18                 out[7] <= in;
  19 `endif
  20         end
  21
  22 endmodule