tests/arch/common/memory_attributes/attributes_test.v

   1 `default_nettype none
   2 module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10)
   3    (input  wire                      write_enable, clk,
   4     input  wire  [DATA_WIDTH-1:0]    data_in,
   5     input  wire  [ADDRESS_WIDTH-1:0] address_in,
   6     output wire  [DATA_WIDTH-1:0]    data_out);
   7
   8    localparam WORD  = (DATA_WIDTH-1);
   9    localparam DEPTH = (2**ADDRESS_WIDTH-1);
  10
  11    reg [WORD:0] data_out_r;
  12    reg [WORD:0] memory [0:DEPTH];
  13
  14    always @(posedge clk) begin
  15       if (write_enable)
  16         memory[address_in] <= data_in;
  17       data_out_r <= memory[address_in];
  18    end
  19
  20    assign data_out = data_out_r;
  21 endmodule // block_ram
  22
  23 `default_nettype none
  24 module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
  25    (input  wire                      write_enable, clk,
  26     input  wire  [DATA_WIDTH-1:0]    data_in,
  27     input  wire  [ADDRESS_WIDTH-1:0] address_in,
  28     output wire  [DATA_WIDTH-1:0]    data_out);
  29
  30    localparam WORD  = (DATA_WIDTH-1);
  31    localparam DEPTH = (2**ADDRESS_WIDTH-1);
  32
  33    reg [WORD:0] data_out_r;
  34    reg [WORD:0] memory [0:DEPTH];
  35
  36    always @(posedge clk) begin
  37       if (write_enable)
  38         memory[address_in] <= data_in;
  39       data_out_r <= memory[address_in];
  40    end
  41
  42    assign data_out = data_out_r;
  43 endmodule // distributed_ram
  44
  45 `default_nettype none
  46 module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
  47    (input  wire                      write_enable, clk,
  48     input  wire  [DATA_WIDTH-1:0]    data_in,
  49     input  wire  [ADDRESS_WIDTH-1:0] address_in,
  50     output wire  [DATA_WIDTH-1:0]    data_out);
  51
  52    localparam WORD  = (DATA_WIDTH-1);
  53    localparam DEPTH = (2**ADDRESS_WIDTH-1);
  54
  55    reg [WORD:0] data_out_r;
  56    (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH];
  57
  58    always @(posedge clk) begin
  59       if (write_enable)
  60         memory[address_in] <= data_in;
  61       data_out_r <= memory[address_in];
  62    end
  63
  64    assign data_out = data_out_r;
  65 endmodule // distributed_ram
  66
  67 `default_nettype none
  68 module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
  69    (input  wire                      write_enable, clk,
  70     input  wire  [DATA_WIDTH-1:0]    data_in,
  71     input  wire  [ADDRESS_WIDTH-1:0] address_in,
  72     output wire  [DATA_WIDTH-1:0]    data_out);
  73
  74    localparam WORD  = (DATA_WIDTH-1);
  75    localparam DEPTH = (2**ADDRESS_WIDTH-1);
  76
  77    reg [WORD:0] data_out_r;
  78    (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH];
  79
  80    always @(posedge clk) begin
  81       if (write_enable)
  82         memory[address_in] <= data_in;
  83       data_out_r <= memory[address_in];
  84    end
  85
  86    assign data_out = data_out_r;
  87 endmodule // distributed_ram
  88