tests/arch/ecp5/latches_abc9.ys

   1 read_verilog <<EOT
   2 module top(input e, d, output q);
   3 reg l;
   4 always @*
   5     if (e)
   6         l = ~d;
   7 assign q = ~l;
   8 endmodule
   9 EOT
  10 proc
  11 design -save gold
  12
  13 # Can't run any sort of equivalence check because latches are blown to LUTs
  14 synth_ecp5 -abc9
  15 select -assert-count 2 t:LUT4
  16 select -assert-none t:LUT4 %% t:* %D