tests/arch/nexus/mux.ys

   1 read_verilog ../common/mux.v
   2 design -save read
   3
   4 hierarchy -top mux2
   5 proc
   6 equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
   7 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
   8 cd mux2 # Constrain all select calls below inside the top module
   9 select -assert-count 1 t:LUT4
  10 select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D
  11
  12 design -load read
  13 hierarchy -top mux4
  14 proc
  15 equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
  16 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
  17 cd mux4 # Constrain all select calls below inside the top module
  18 select -assert-count 1 t:WIDEFN9
  19
  20 select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D
  21
  22 design -load read
  23 hierarchy -top mux8
  24 proc
  25 equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
  26 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
  27 cd mux8 # Constrain all select calls below inside the top module
  28 select -assert-count 4 t:LUT4
  29 select -assert-count 1 t:WIDEFN9
  30
  31 select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D
  32
  33 design -load read
  34 hierarchy -top mux16
  35 proc
  36 equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
  37 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
  38 cd mux16 # Constrain all select calls below inside the top module
  39 select -assert-min 11 t:LUT4
  40 select -assert-max 12 t:LUT4
  41 select -assert-count 1 t:WIDEFN9
  42
  43 select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D