Add simcells.v, simlib.v, and some output
[yosys.git] / tests / arch / run-test.sh
1 #!/bin/bash
2
3 set -e
4
5 echo "Running syntax check on arch sim models"
6 for arch in ../../techlibs/*; do
7 find $arch -name cells_sim.v | while read path; do
8 echo -n "Test $path ->"
9 iverilog -t null -I$arch $path
10 echo " ok"
11 done
12 done
13
14 for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
15 echo -n "Test $path ->"
16 iverilog -t null $path
17 echo " ok"
18 done