tests/arch/xilinx/dffs.ys

   1 read_verilog ../common/dffs.v
   2 design -save read
   3
   4 hierarchy -top dff
   5 proc
   6 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
   7 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
   8 cd dff # Constrain all select calls below inside the top module
   9 select -assert-count 1 t:BUFG
  10 select -assert-count 1 t:FDRE
  11 select -assert-none t:BUFG t:FDRE %% t:* %D
  12
  13
  14 design -load read
  15 hierarchy -top dffe
  16 proc
  17 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
  18 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
  19 cd dffe # Constrain all select calls below inside the top module
  20 select -assert-count 1 t:BUFG
  21 select -assert-count 1 t:FDRE
  22 select -assert-none t:BUFG t:FDRE %% t:* %D
  23
  24
  25 design -load read
  26 hierarchy -top dff
  27 proc
  28 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
  29 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
  30 cd dff # Constrain all select calls below inside the top module
  31 select -assert-count 1 t:BUFG
  32 select -assert-count 1 t:FDRE
  33 select -assert-none t:BUFG t:FDRE %% t:* %D
  34
  35
  36 design -load read
  37 hierarchy -top dffe
  38 proc
  39 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
  40 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
  41 cd dffe # Constrain all select calls below inside the top module
  42 select -assert-count 1 t:BUFG
  43 select -assert-count 1 t:FDRE
  44 select -assert-none t:BUFG t:FDRE %% t:* %D
  45