sv: support declaration in generate for initialization
[yosys.git] / tests / asicworld / code_hdl_models_GrayCounter.v
1 //==========================================
2 // Function : Code Gray counter.
3 // Coder : Alex Claros F.
4 // Date : 15/May/2005.
5 //=======================================
6
7 module GrayCounter
8 #(parameter COUNTER_WIDTH = 4)
9
10 (output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
11
12 input wire Enable_in, //Count enable.
13 input wire Clear_in, //Count reset.
14
15 input wire Clk);
16
17 /////////Internal connections & variables///////
18 reg [COUNTER_WIDTH-1:0] BinaryCount;
19
20 /////////Code///////////////////////
21
22 always @ (posedge Clk)
23 if (Clear_in) begin
24 BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
25 GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
26 end
27 else if (Enable_in) begin
28 BinaryCount <= BinaryCount + 1;
29 GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
30 BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
31 end
32
33 endmodule