tests/asicworld/code_hdl_models_arbiter_tb.v

   1 module testbench ();
   2
   3 reg             clk = 0;
   4 reg             rst = 1;
   5 reg             req3 = 0;
   6 reg             req2 = 0;
   7 reg             req1 = 0;
   8 reg             req0 = 0;
   9 wire            gnt3;
  10 wire            gnt2;
  11 wire            gnt1;
  12 wire            gnt0;
  13
  14 // Clock generator
  15 always #1 clk = ~clk;
  16 integer file;
  17
  18 always @(posedge clk)
  19   $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});
  20
  21 initial begin
  22   file = $fopen(`outfile);
  23   repeat (5) @ (posedge clk);
  24   rst <= 0;
  25   repeat (1) @ (posedge clk);
  26   req0 <= 1;
  27   repeat (1) @ (posedge clk);
  28   req0 <= 0;
  29   repeat (1) @ (posedge clk);
  30   req0 <= 1;
  31   req1 <= 1;
  32   repeat (1) @ (posedge clk);
  33   req2 <= 1;
  34   req1 <= 0;
  35   repeat (1) @ (posedge clk);
  36   req3 <= 1;
  37   req2 <= 0;
  38   repeat (1) @ (posedge clk);
  39   req3 <= 0;
  40   repeat (1) @ (posedge clk);
  41   req0 <= 0;
  42   repeat (1) @ (posedge clk);
  43   #10 $finish;
  44 end
  45
  46 // Connect the DUT
  47 arbiter U (
  48  clk,
  49  rst,
  50  req3,
  51  req2,
  52  req1,
  53  req0,
  54  gnt3,
  55  gnt2,
  56  gnt1,
  57  gnt0
  58 );
  59
  60 endmodule