1 //-----------------------------------------------------
2 // Design Name : clk_div_45
3 // File Name : clk_div_45.v
4 // Function : Divide by 4.5
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
9 enable, // Enable is sync with falling edge of clk_in
10 clk_out // Output Clock
13 // --------------Port Declaration-----------------------
18 //--------------Port data type declaration-------------
23 //--------------Internal Registers----------------------
29 //--------------Code Starts Here-----------------------
30 always @ (posedge clk_in)
31 if (enable == 1'b0) begin
34 end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
38 counter1 <= counter1 + 1;
41 always @ (negedge clk_in)
42 if (enable == 1'b0) begin
45 end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4)) begin
49 counter2 <= counter2 + 1;
52 assign clk_out = (counter1 <3 && counter2 < 3) & enable;