tests/asicworld/code_hdl_models_clk_div_45.v

   1 //-----------------------------------------------------
   2 // Design Name : clk_div_45
   3 // File Name   : clk_div_45.v
   4 // Function    : Divide by 4.5
   5 // Coder       : Deepak Kumar Tala
   6 //-----------------------------------------------------
   7 module clk_div_45 (
   8 clk_in, // Input Clock
   9 enable, // Enable is sync with falling edge of clk_in
  10 clk_out // Output Clock
  11 );
  12
  13 // --------------Port Declaration-----------------------
  14 input      clk_in     ;
  15 input      enable     ;
  16 output     clk_out    ;
  17
  18 //--------------Port data type declaration-------------
  19 wire       clk_in     ;
  20 wire       enable     ;
  21 wire       clk_out    ;
  22
  23 //--------------Internal Registers----------------------
  24 reg   [3:0] counter1   ;
  25 reg   [3:0] counter2   ;
  26 reg         toggle1    ;
  27 reg         toggle2    ;
  28
  29 //--------------Code Starts Here-----------------------
  30 always @ (posedge clk_in)
  31 if (enable == 1'b0) begin
  32    counter1 <= 4'b0;
  33    toggle1  <= 0;
  34 end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4))  begin
  35    counter1 <= 4'b0;
  36    toggle1  <= ~toggle1;
  37 end else   begin
  38    counter1 <= counter1 + 1;
  39 end
  40
  41 always @ (negedge clk_in)
  42 if (enable == 1'b0) begin
  43   counter2 <= 4'b0;
  44   toggle2  <= 0;
  45 end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4))  begin
  46   counter2 <= 4'b0;
  47   toggle2  <= ~toggle2;
  48 end  else   begin
  49   counter2 <= counter2 + 1;
  50 end
  51
  52 assign  clk_out = (counter1 <3 && counter2 < 3) & enable;
  53
  54 endmodule