tests/asicworld/code_hdl_models_d_latch_gates.v

   1 module d_latch_gates(d,clk,q,q_bar);
   2 input d,clk;
   3 output q, q_bar;
   4
   5 wire n1,n2,n3;
   6
   7 not (n1,d);
   8
   9 nand (n2,d,clk);
  10 nand (n3,n1,clk);
  11
  12 nand (q,q_bar,n2);
  13 nand (q_bar,q,n3);
  14
  15 endmodule