tests/asicworld/code_hdl_models_decoder_2to4_gates.v

   1 module decoder_2to4_gates (x,y,f0,f1,f2,f3);
   2 input x,y;
   3 output f0,f1,f2,f3;
   4
   5 wire n1,n2;
   6
   7 not i1 (n1,x);
   8 not i2 (n2,y);
   9 and a1 (f0,n1,n2);
  10 and a2 (f1,n1,y);
  11 and a3 (f2,x,n2);
  12 and a4 (f3,x,y);
  13
  14 endmodule