sv: support declaration in generate for initialization
[yosys.git] / tests / asicworld / code_hdl_models_decoder_using_assign.v
1 //-----------------------------------------------------
2 // Design Name : decoder_using_assign
3 // File Name : decoder_using_assign.v
4 // Function : decoder using assign
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module decoder_using_assign (
8 binary_in , // 4 bit binary input
9 decoder_out , // 16-bit out
10 enable // Enable for the decoder
11 );
12 input [3:0] binary_in ;
13 input enable ;
14 output [15:0] decoder_out ;
15
16 wire [15:0] decoder_out ;
17
18 assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
19
20 endmodule