Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git] / tests / asicworld / code_hdl_models_decoder_using_case.v
1 //-----------------------------------------------------
2 // Design Name : decoder_using_case
3 // File Name : decoder_using_case.v
4 // Function : decoder using case
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module decoder_using_case (
8 binary_in , // 4 bit binary input
9 decoder_out , // 16-bit out
10 enable // Enable for the decoder
11 );
12 input [3:0] binary_in ;
13 input enable ;
14 output [15:0] decoder_out ;
15
16 reg [15:0] decoder_out ;
17
18 always @ (enable or binary_in)
19 begin
20 decoder_out = 0;
21 if (enable) begin
22 case (binary_in)
23 4'h0 : decoder_out = 16'h0001;
24 4'h1 : decoder_out = 16'h0002;
25 4'h2 : decoder_out = 16'h0004;
26 4'h3 : decoder_out = 16'h0008;
27 4'h4 : decoder_out = 16'h0010;
28 4'h5 : decoder_out = 16'h0020;
29 4'h6 : decoder_out = 16'h0040;
30 4'h7 : decoder_out = 16'h0080;
31 4'h8 : decoder_out = 16'h0100;
32 4'h9 : decoder_out = 16'h0200;
33 4'hA : decoder_out = 16'h0400;
34 4'hB : decoder_out = 16'h0800;
35 4'hC : decoder_out = 16'h1000;
36 4'hD : decoder_out = 16'h2000;
37 4'hE : decoder_out = 16'h4000;
38 4'hF : decoder_out = 16'h8000;
39 endcase
40 end
41 end
42
43 endmodule