tests/asicworld/code_hdl_models_encoder_4to2_gates.v

   1 module encoder_4to2_gates (i0,i1,i2,i3,y);
   2 input i0,i1,i2,i3;
   3 output [1:0] y;
   4
   5 or o1 (y[0],i1,i3);
   6 or o2 (y[1],i2,i3);
   7
   8 endmodule