tests/asicworld/code_hdl_models_gray_counter.v

   1 //-----------------------------------------------------
   2 // Design Name : gray_counter
   3 // File Name   : gray_counter.v
   4 // Function    : 8 bit gray counterS
   5 // Coder       : Deepak Kumar Tala
   6 //-----------------------------------------------------
   7 module gray_counter (
   8   out    , // counter out
   9   enable , // enable for counter
  10   clk    , // clock
  11   rst      // active hight reset
  12   );
  13
  14   //------------Input Ports--------------
  15   input clk, rst, enable;
  16   //----------Output Ports----------------
  17   output [ 7:0] out;
  18   //------------Internal Variables--------
  19   wire [7:0] out;
  20   reg [7:0] count;
  21   //-------------Code Starts Here---------
  22   always @ (posedge clk)
  23   if (rst)
  24     count <= 0;
  25   else if (enable)
  26     count <= count + 1;
  27
  28   assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
  29                count[5]),(count[5] ^ count[4]), (count[4] ^
  30                count[3]),(count[3] ^ count[2]), (count[2] ^
  31                count[1]),(count[1] ^ count[0]) };
  32
  33 endmodule