tests/asicworld/code_hdl_models_half_adder_gates.v

   1 //-----------------------------------------------------
   2 // Design Name : half_adder_gates
   3 // File Name   : half_adder_gates.v
   4 // Function    : CCITT Serial CRC
   5 // Coder       : Deepak Kumar Tala
   6 //-----------------------------------------------------
   7 module half_adder_gates(x,y,sum,carry);
   8 input x,y;
   9 output sum,carry;
  10
  11 and U_carry (carry,x,y);
  12 xor U_sum (sum,x,y);
  13
  14 endmodule