tests/asicworld/code_hdl_models_one_hot_cnt.v

   1 //-----------------------------------------------------
   2 // Design Name : one_hot_cnt
   3 // File Name   : one_hot_cnt.v
   4 // Function    : 8 bit one hot counter
   5 // Coder       : Deepak Kumar Tala
   6 //-----------------------------------------------------
   7 module one_hot_cnt (
   8 out        ,  // Output of the counter
   9 enable     ,  // enable for counter
  10 clk        ,  // clock input
  11 reset         // reset input
  12 );
  13 //----------Output Ports--------------
  14 output [7:0] out;
  15
  16 //------------Input Ports--------------
  17 input enable, clk, reset;
  18
  19 //------------Internal Variables--------
  20 reg [7:0] out;
  21
  22 //-------------Code Starts Here-------
  23 always @ (posedge clk)
  24 if (reset) begin
  25   out <= 8'b0000_0001 ;
  26 end else if (enable) begin
  27   out <= {out[6],out[5],out[4],out[3],
  28           out[2],out[1],out[0],out[7]};
  29 end
  30
  31 endmodule