Add a couple more tests
[yosys.git] / tests / asicworld / code_hdl_models_parity_using_assign.v
1 //-----------------------------------------------------
2 // Design Name : parity_using_assign
3 // File Name : parity_using_assign.v
4 // Function : Parity using assign
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module parity_using_assign (
8 data_in , // 8 bit data in
9 parity_out // 1 bit parity out
10 );
11 output parity_out ;
12 input [7:0] data_in ;
13
14 wire parity_out ;
15
16 assign parity_out = (data_in[0] ^ data_in[1]) ^
17 (data_in[2] ^ data_in[3]) ^
18 (data_in[4] ^ data_in[5]) ^
19 (data_in[6] ^ data_in[7]);
20
21 endmodule