Add a couple more tests
[yosys.git] / tests / asicworld / code_hdl_models_parity_using_bitwise.v
1 //-----------------------------------------------------
2 // Design Name : parity_using_bitwise
3 // File Name : parity_using_bitwise.v
4 // Function : Parity using bitwise xor
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module parity_using_bitwise (
8 data_in , // 8 bit data in
9 parity_out // 1 bit parity out
10 );
11 output parity_out ;
12 input [7:0] data_in ;
13
14 assign parity_out = ^data_in;
15
16 endmodule