1 //-----------------------------------------------------
4 // Function : Simple UART
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
32 output [7:0] rx_data ;
45 reg [3:0] rx_sample_cnt ;
55 always @ (posedge rxclk or posedge reset)
68 // Synchronize the asynch signal
72 if (uld_rx_data) begin
76 // Receive data only when rx is enabled
78 // Check if just received start of frame
79 if (!rx_busy && !rx_d2) begin
84 // Start of frame detected, Proceed with rest of data
86 rx_sample_cnt <= rx_sample_cnt + 1;
87 // Logic to sample at middle of data
88 if (rx_sample_cnt == 7) begin
89 if ((rx_d2 == 1) && (rx_cnt == 0)) begin
93 // Start storing the rx data
94 if (rx_cnt > 0 && rx_cnt < 9) begin
95 rx_reg[rx_cnt - 1] <= rx_d2;
97 if (rx_cnt == 9) begin
99 // Check if End of frame received correctly
100 if (rx_d2 == 0) begin
105 // Check if last rx data was not unloaded,
106 rx_over_run <= (rx_empty) ? 0 : 1;
113 if (!rx_enable) begin
119 always @ (posedge txclk or posedge reset)
127 if (ld_tx_data) begin
135 if (tx_enable && !tx_empty) begin
136 tx_cnt <= tx_cnt + 1;
137 if (tx_cnt == 0) begin
140 if (tx_cnt > 0 && tx_cnt < 9) begin
141 tx_out <= tx_reg[tx_cnt -1];
143 if (tx_cnt == 9) begin
149 if (!tx_enable) begin