tests/asicworld/code_hdl_models_up_counter_load.v

   1 //-----------------------------------------------------
   2 // Design Name : up_counter_load
   3 // File Name   : up_counter_load.v
   4 // Function    : Up counter with load
   5 // Coder       : Deepak Kumar Tala
   6 //-----------------------------------------------------
   7 module up_counter_load    (
   8 out      ,  // Output of the counter
   9 data     ,  // Parallel load for the counter
  10 load     ,  // Parallel load enable
  11 enable   ,  // Enable counting
  12 clk      ,  // clock input
  13 reset       // reset input
  14 );
  15 //----------Output Ports--------------
  16 output [7:0] out;
  17 //------------Input Ports--------------
  18 input [7:0] data;
  19 input load, enable, clk, reset;
  20 //------------Internal Variables--------
  21 reg [7:0] out;
  22 //-------------Code Starts Here-------
  23 always @(posedge clk)
  24 if (reset) begin
  25   out <= 8'b0 ;
  26 end else if (load) begin
  27   out <= data;
  28 end else if (enable) begin
  29   out <= out + 1;
  30 end
  31
  32 endmodule