tests/asicworld/code_hdl_models_up_down_counter.v

   1 //-----------------------------------------------------
   2 // Design Name : up_down_counter
   3 // File Name   : up_down_counter.v
   4 // Function    : Up down counter
   5 // Coder       : Deepak Kumar Tala
   6 //-----------------------------------------------------
   7 module up_down_counter    (
   8 out      ,  // Output of the counter
   9 up_down  ,  // up_down control for counter
  10 clk      ,  // clock input
  11 reset       // reset input
  12 );
  13 //----------Output Ports--------------
  14 output [7:0] out;
  15 //------------Input Ports--------------
  16 input up_down, clk, reset;
  17 //------------Internal Variables--------
  18 reg [7:0] out;
  19 //-------------Code Starts Here-------
  20 always @(posedge clk)
  21 if (reset) begin // active high reset
  22   out <= 8'b0 ;
  23 end else if (up_down) begin
  24   out <= out + 1;
  25 end else begin
  26   out <= out - 1;
  27 end
  28
  29 endmodule