2 clk, reset, data_in0, data_in1, data_in2,
3 data_in3, data_in4, data_in5, data_in_valid0,
4 data_in_valid1, data_in_valid2, data_in_valid3,
5 data_in_valid4, data_in_valid5, data_out0,
6 data_out1, data_out2, data_out3, data_out4,
7 data_out5, data_out_ack0, data_out_ack1,
8 data_out_ack2, data_out_ack3, data_out_ack4,
13 input [7:0] data_in0, data_in1, data_in2, data_in3;
14 input [7:0] data_in4, data_in5;
15 input data_in_valid0, data_in_valid1, data_in_valid2;
16 input [7:0] data_in_valid3, data_in_valid4, data_in_valid5;
17 output [7:0] data_out0, data_out1, data_out2, data_out3;
18 output [7:0] data_out4, data_out5;
19 output data_out_ack0, data_out_ack1, data_out_ack2;
20 output [7:0] data_out_ack3, data_out_ack4, data_out_ack5;
25 switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
26 .data_in_valid(data_in_valid0), .data_out(data_out0),
27 .data_out_ack(data_out_ack0));
29 switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
30 .data_in_valid(data_in_valid1), .data_out(data_out1),
31 .data_out_ack(data_out_ack1));
33 switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
34 .data_in_valid(data_in_valid2), .data_out(data_out2), .
35 data_out_ack(data_out_ack2));
37 switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
38 .data_in_valid(data_in_valid3), .data_out(data_out3),
39 .data_out_ack(data_out_ack3));
41 switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
42 .data_in_valid(data_in_valid4), .data_out(data_out4),
43 .data_out_ack(data_out_ack4));
45 switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
46 .data_in_valid(data_in_valid5), .data_out(data_out5),
47 .data_out_ack(data_out_ack5));
64 output [7:0] data_out;
70 always @ (posedge clk)
74 end else if (data_in_valid) begin