tests/asicworld/code_specman_switch_fabric.v

   1 module switch_fabric(
   2   clk, reset, data_in0, data_in1, data_in2,
   3   data_in3, data_in4, data_in5, data_in_valid0,
   4   data_in_valid1, data_in_valid2, data_in_valid3,
   5   data_in_valid4, data_in_valid5, data_out0,
   6   data_out1, data_out2, data_out3, data_out4,
   7   data_out5, data_out_ack0, data_out_ack1,
   8   data_out_ack2, data_out_ack3, data_out_ack4,
   9   data_out_ack5
  10 );
  11
  12 input           clk, reset;
  13 input  [7:0]    data_in0, data_in1, data_in2, data_in3;
  14 input  [7:0]    data_in4, data_in5;
  15 input           data_in_valid0, data_in_valid1, data_in_valid2;
  16 input  [7:0]    data_in_valid3, data_in_valid4, data_in_valid5;
  17 output [7:0]    data_out0, data_out1, data_out2, data_out3;
  18 output [7:0]    data_out4, data_out5;
  19 output          data_out_ack0, data_out_ack1, data_out_ack2;
  20 output [7:0]    data_out_ack3, data_out_ack4, data_out_ack5;
  21
  22 (* gentb_clock *)
  23 wire clk;
  24
  25 switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
  26   .data_in_valid(data_in_valid0), .data_out(data_out0),
  27   .data_out_ack(data_out_ack0));
  28
  29 switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
  30   .data_in_valid(data_in_valid1), .data_out(data_out1),
  31   .data_out_ack(data_out_ack1));
  32
  33 switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
  34   .data_in_valid(data_in_valid2), .data_out(data_out2), .
  35   data_out_ack(data_out_ack2));
  36
  37 switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
  38   .data_in_valid(data_in_valid3), .data_out(data_out3),
  39   .data_out_ack(data_out_ack3));
  40
  41 switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
  42   .data_in_valid(data_in_valid4), .data_out(data_out4),
  43   .data_out_ack(data_out_ack4));
  44
  45 switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
  46   .data_in_valid(data_in_valid5), .data_out(data_out5),
  47   .data_out_ack(data_out_ack5));
  48
  49 endmodule
  50
  51 module switch (
  52   clk,
  53   reset,
  54   data_in,
  55   data_in_valid,
  56   data_out,
  57   data_out_ack
  58 );
  59
  60 input   clk;
  61 input   reset;
  62 input [7:0]  data_in;
  63 input   data_in_valid;
  64 output [7:0]  data_out;
  65 output  data_out_ack;
  66
  67 reg [7:0]  data_out;
  68 reg   data_out_ack;
  69
  70 always @ (posedge clk)
  71 if (reset) begin
  72    data_out <= 0;
  73    data_out_ack <= 0;
  74 end else if (data_in_valid) begin
  75    data_out <= data_in;
  76    data_out_ack <= 1;
  77 end else begin
  78    data_out <= 0;
  79    data_out_ack <= 0;
  80 end
  81
  82 endmodule