tests/asicworld/code_tidbits_asyn_reset.v

   1 module  asyn_reset(clk,reset,a,c);
   2      input clk;
   3      input reset;
   4      input a;
   5      output c;
   6
   7    wire clk;
   8    wire reset;
   9    wire a;
  10    reg c;
  11
  12 always @ (posedge clk or posedge reset)
  13  if ( reset == 1'b1) begin
  14    c <= 0;
  15  end else begin
  16    c <= a;
  17  end
  18 endmodule