tests/asicworld/code_tidbits_blocking.v

   1 module blocking (clk,a,c);
   2 input clk;
   3 input a;
   4 output c;
   5
   6 wire clk;
   7 wire a;
   8 reg c;
   9 reg b;
  10
  11 always @ (posedge clk )
  12 begin
  13  b = a;
  14  c = b;
  15 end
  16
  17 endmodule