1 //-----------------------------------------------------
2 // This is FSM demo program using always block
3 // Design Name : fsm_using_always
4 // File Name : fsm_using_always.v
5 //-----------------------------------------------------
6 module fsm_using_always (
8 reset , // Active high, syn reset
14 //-------------Input Ports-----------------------------
15 input clock,reset,req_0,req_1;
16 //-------------Output Ports----------------------------
18 //-------------Input ports Data Type-------------------
19 wire clock,reset,req_0,req_1;
20 //-------------Output Ports Data Type------------------
22 //-------------Internal Constants--------------------------
24 parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
25 //-------------Internal Variables---------------------------
26 reg [SIZE-1:0] state ;// Seq part of the FSM
27 reg [SIZE-1:0] next_state ;// combo part of FSM
28 //----------Code startes Here------------------------
29 always @ (state or req_0 or req_1)
33 IDLE : if (req_0 == 1'b1) begin
35 end else if (req_1 == 1'b1) begin
40 GNT0 : if (req_0 == 1'b1) begin
45 GNT1 : if (req_1 == 1'b1) begin
50 default : next_state = IDLE;
53 //----------Seq Logic-----------------------------
54 always @ (posedge clock)
56 if (reset == 1'b1) begin
59 state <= #1 next_state;
62 //----------Output Logic-----------------------------
63 always @ (posedge clock)
65 if (reset == 1'b1) begin
89 end // End Of Block OUTPUT_LOGIC
91 endmodule // End of Module arbiter