tests/asicworld/code_tidbits_fsm_using_always.v

   1 //-----------------------------------------------------
   2 // This is FSM demo program using always block
   3 // Design Name : fsm_using_always
   4 // File Name   : fsm_using_always.v
   5 //-----------------------------------------------------
   6 module fsm_using_always (
   7 clock      , // clock
   8 reset      , // Active high, syn reset
   9 req_0      , // Request 0
  10 req_1      , // Request 1
  11 gnt_0      , // Grant 0
  12 gnt_1
  13 );
  14 //-------------Input Ports-----------------------------
  15 input   clock,reset,req_0,req_1;
  16  //-------------Output Ports----------------------------
  17 output  gnt_0,gnt_1;
  18 //-------------Input ports Data Type-------------------
  19 wire    clock,reset,req_0,req_1;
  20 //-------------Output Ports Data Type------------------
  21 reg     gnt_0,gnt_1;
  22 //-------------Internal Constants--------------------------
  23 parameter SIZE = 3           ;
  24 parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
  25 //-------------Internal Variables---------------------------
  26 reg   [SIZE-1:0]          state        ;// Seq part of the FSM
  27 reg   [SIZE-1:0]          next_state   ;// combo part of FSM
  28 //----------Code startes Here------------------------
  29 always @ (state or req_0 or req_1)
  30 begin : FSM_COMBO
  31  next_state = 3'b000;
  32  case(state)
  33    IDLE : if (req_0 == 1'b1) begin
  34                 next_state = GNT0;
  35               end else if (req_1 == 1'b1) begin
  36                 next_state= GNT1;
  37               end else begin
  38                 next_state = IDLE;
  39               end
  40    GNT0 : if (req_0 == 1'b1) begin
  41                 next_state = GNT0;
  42               end else begin
  43                 next_state = IDLE;
  44               end
  45    GNT1 : if (req_1 == 1'b1) begin
  46                 next_state = GNT1;
  47               end else begin
  48                 next_state = IDLE;
  49               end
  50    default : next_state = IDLE;
  51   endcase
  52 end
  53 //----------Seq Logic-----------------------------
  54 always @ (posedge clock)
  55 begin : FSM_SEQ
  56   if (reset == 1'b1) begin
  57     state <= #1 IDLE;
  58   end else begin
  59     state <= #1 next_state;
  60   end
  61 end
  62 //----------Output Logic-----------------------------
  63 always @ (posedge clock)
  64 begin : OUTPUT_LOGIC
  65 if (reset == 1'b1) begin
  66   gnt_0 <= #1 1'b0;
  67   gnt_1 <= #1 1'b0;
  68 end
  69 else begin
  70   case(state)
  71     IDLE : begin
  72                   gnt_0 <= #1 1'b0;
  73                   gnt_1 <= #1 1'b0;
  74                end
  75    GNT0 : begin
  76                    gnt_0 <= #1 1'b1;
  77                    gnt_1 <= #1 1'b0;
  78                 end
  79    GNT1 : begin
  80                    gnt_0 <= #1 1'b0;
  81                    gnt_1 <= #1 1'b1;
  82                 end
  83    default : begin
  84                     gnt_0 <= #1 1'b0;
  85                     gnt_1 <= #1 1'b0;
  86                   end
  87   endcase
  88 end
  89 end // End Of Block OUTPUT_LOGIC
  90
  91 endmodule // End of Module arbiter