1 //-----------------------------------------------------
2 // This is FSM demo program using function
3 // Design Name : fsm_using_function
4 // File Name : fsm_using_function.v
5 //-----------------------------------------------------
6 module fsm_using_function (
8 reset , // Active high, syn reset
14 //-------------Input Ports-----------------------------
15 input clock,reset,req_0,req_1;
16 //-------------Output Ports----------------------------
18 //-------------Input ports Data Type-------------------
19 wire clock,reset,req_0,req_1;
20 //-------------Output Ports Data Type------------------
22 //-------------Internal Constants--------------------------
24 parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
25 //-------------Internal Variables---------------------------
26 reg [SIZE-1:0] state ;// Seq part of the FSM
27 wire [SIZE-1:0] next_state ;// combo part of FSM
28 //----------Code startes Here------------------------
29 assign next_state = fsm_function(state, req_0, req_1);
30 //----------Function for Combo Logic-----------------
31 function [SIZE-1:0] fsm_function;
32 input [SIZE-1:0] state ;
36 IDLE : if (req_0 == 1'b1) begin
38 end else if (req_1 == 1'b1) begin
43 GNT0 : if (req_0 == 1'b1) begin
48 GNT1 : if (req_1 == 1'b1) begin
53 default : fsm_function = IDLE;
56 //----------Seq Logic-----------------------------
57 always @ (posedge clock)
59 if (reset == 1'b1) begin
62 state <= #1 next_state;
65 //----------Output Logic-----------------------------
66 always @ (posedge clock)
68 if (reset == 1'b1) begin
92 end // End Of Block OUTPUT_LOGIC
94 endmodule // End of Module arbiter